1. Field of the Invention
The present invention relates to a TTL logic circuit, and more specifically to a Bi-CMOS type TTL logic circuit.
2. Description of the Prior Art
Referring now to FIG. 1, an arrangement is illustrated of an output circuit section of a TTL logic circuit having a Schottky diode realized by a Bi-CMOS technique.
An input signal "A" from an input terminal 20 is fed to gate terminals of a P channel MOS transistor 9 and an N channel MOS transistor 5, and a source output from the MOS transistor 9 drives a base of an NPN Schottky barrier diode-equipped bipolar transistor 1 through resistance 11. The MOS transistor 5 disposed between the base of the transistor 1 and ground potential is to quickly discharge electric charges residual on the base of the transistor 1 for speeding-up cut-off operation of the transistor.
The transistor 1 has its collector connected with a resistor 12 through which a collector driving current of the transistor 1 is fed. The transistor 1 further has its emitter connected with one end of a resistor 13 which is further connected with ground at the other end, and connected with a base of an NPN type Shottky barrier diode-equipped bipolar transistor 2 which is driven by an output of the emitter of the transistor 1. The transistor 2 provides a circuit output 30 on its collector. An N channel MOS transistor 6 is provided for quickly discharging residual electric charges remaining on the base of the transistor 2, to a gate of which transistor 6 the input signal "A" is applied.
A low level of the circuit output is determined by the transistors 1 and 2, and a high level of the same is determined by NPN bipolar transistors 3, 4 which are interconnected in Darlington construction. For driving the transistors 3 and 4 are provided an inverter 15 for inverting the input signal "A" and a CMOS inverter (a combination of a P channel transistor 10 and an N channel transistor 7) for further inverting an output of the inverter 15, an output of the CMOS inverter is applied to a base of the transistor 3. An emitter output of the transistor 4 provides the circuit output 30. Herein, the transistor 7 has a function to quickly discharge electric charges residual on the basis of the transistor 3.
For quickly discharging electric charges residual on a base of the transistor 4, an N channel MOS transistor 8 is provided, to a gate of which the output of the inverter 15 is applied. The transistor 4 has its collector connected with a Schottky barrier diode 14 for protecting the transistors 3, 4 when any load (not shown) is short-circuitted.
The above prior art TTL logic circuit is constructed such that the high and low levels of the circuit output 30 are completely isolated by the CMOS transistor to greatly reduce power consumption of the circuit particularly the power upon a high level output being provided.
The prior art circuit is further constructed such that for preventing saturated operations of the transistors 1, 2 upon a low level output being provided both collector potentials are clamped by the Shottky barrier diode and a clamped current is limited by the resistors 11 through 13.
In order to speed up the operation of the prior art circuit the following techniques are considered:
(1) Resistances 11 and 12 are reduced to increase a current flowing through the NPN transistor 1.
(2) The gate width of the P channel MOS transistor 9 is extended to increase the current flowing through the NPN transistor 1.
(3) The gate widths of the N channel MOS transistors 5 through 8 are extended to further speed up the cut-off of the NPN transistors 1 through 4.
(4) The gate widths of the P channel MOS transistor 10 and the N channel MOS transistor 7 are both extended.
The technique (2) is less effective because on-resistance of the P channel MOS transistor 9 is typically several hundred ohms whilst the resistance 11 is several kilo ohms, considerably greater than the on-resistance.
The techniques (3) and (4) are unsuccessful because of an increase of paracitic source-drain capacitance due to the extension of the gate width as well as an increase of the number of elements (an increase of an element area as a result of the extension of the gate width.). It is therefore the present state of the prior art circuit to design a circuit so as to optimize an interrelation between the power consumption and the operating speed using the technique (1).
In the prior art TTL circuit, an interrelation is existent between the power consumption and the operating speed hence it is impossible to satisfactorily improve the operating speed even though the operating speed and the power consumption are made optimum independently.
For instance, in FIG. 1, with the resistances 11 and 12 being reduced the operating speed is improved but simultaneously the power consumption is also increased. A current flowing through the circuit at the low level output being stationary is expressed by: EQU Icc=(Vcc-(2V.sub.B E -V.sub.S B))/R12+(Vcc-2V.sub.B E)/R11,
where V.sub.B E, denotes base-emitter forward voltages of the NPN transistors 1 and 2, V.sub.S B forward voltage of the Schottky barrier diode equipment in the transistors 1, 2, Vcc power supply voltage, and R11 and R12 denote resistance values of the resistors 11 and 12.
A first term on the right side of the above equation denotes a collector current flowing through the NPN transistor 1, and a second term denotes a base current flowing through the NPN transistor 1. It can be seen from the equation that the power consumption is inversely proportional to the resistance values of the resistors 11 and 12, so that an intension to improve the operating speed causes a severe increase of the power consumption. Thus, an effort to yield practical power consumption impedes a satisfactory improvement of the operating speed.